IRIS MATCHING STEP IMPLEMENTATION IN FPGA

Abstract

Iris recognition system has been recently widely used as it is in the forefront of other biometric systemssince it contains distinctive patterns that give it a powerful strategy to distinguish between persons for identificationpurposes. However, implementation of this system requires large memory capacity and high computational powerdue to the size of the data and the processes on which it is implemented. These factors make the challenge to finda way for running this algorithm in a hardware platform. Efficient design in hardware reduces the execution timeby exploiting the parallelism and pipeline architecture. The present work addressed this issue and the executiontime was actually reduced when implementing iris matching step using hamming distance algorithm on the targetdevice FPGA KINTEX 7 utilizing Xilinx system generator. The obtained result demonstrates that the executiontime has been accelerated to 1.32 ns, which is almost at least four times faster than the existing works.