LOOP UNROLLING IMPLEMENTATION OF AN AES ALGORITHM USING XILINX SYSTEM GENERATOR

Abstract

Cryptographic algorithm is a tool that is used to secure the transmitted data on the network. The currentstandard algorithm the Advanced Encryption Standard (AES) is used to maintain the security and reliability of theencrypted data whether these data are stored in computer or in transmit. AES can be implemented either in hardwareor software, however hardware implementation is more sensible for high speed applications. In this paper, AES- 128algorithm is implemented in hardware in order to achieve a high-speed data processing. It is implemented on anFPGA platform using HLL language and Xilinx ISE software. The design is effectively optimized and Synthesizablewith high accuracy using the conventional blocks of Xilinx System Generator. The results of implementation haveenhanced the performance in terms of resource utilization, speed and power consumption as compared with otherrelated works. The circuit operates at a maximum frequency of 800.000 MHz which offers a high throughput of102.4 Gbps on virtex6 xc6vlx130t- 3ff1156, in addition it occupies only 2,405 slices.