Implementations Of 8x8 DCT And IDCT on Different FPGA Technologies Using the Modified Loeffler Algorithm


In this paper the hardware implementations is investing of 8x8 Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT) on different Field Programmable Gate Array (FPGA) technologies using the modified Loeffler algorithm. The investigations involved simulations, and synthesis of Very High Speed Integrated Circuit Hardware Description Language (VHDL) code utilizing recent FPGA families of Xilinx, Altera, and Lucent. The paper achieving the most demanding real-time requirements of some standardized frame resolutions and rates. Synthesis results for 8-point DCT/IDCT implementations indicate operating frequencies of 50 MHz, 60 MHz, and 22 MHz for the investigated Xilinx, Altera and Lucent FPGA chips, respectively. These frequencies allow 2193 Source Input Format (SIF) and 100 High Definition Television (HDTV) frames to be processed by the Xilinx FPGA. The resulting frame processing rates for Lucent are 877 and 40 for SIF and HDTV, while for Altera they are 647 and 29, respectively. Results indicate that the investigated FPGA implementations would speed DCT based compression algorithms up to frame rates well above the real-time requirements of SIF, International Consulting Committee on Radio & Television (CCIR-TV) and HDTV frame formats.