TY - JOUR ID - TI - FPGA-Based Multi-Core MIPS Processor Design AU - Sarah M. Al-sudany AU - Ahmed S. Al-Araji2, AU - Bassam M. Saeed3 PY - 2021 VL - 21 IS - 2 SP - 16 EP - 35 JO - IRAQI JOURNAL OF COMPUTERS, COMMUNICATIONS, CONTROL AND SYSTEMS ENGINEERING المجلة العراقية لهندسة الحاسبات والاتصالات والسيطرة والنظم SN - 18119212 AB - This research presents a study for multicore Reduced Instruction SetComputer (RISC) processor implemented on the Field Programmable GateArray(FPGA).The Microprocessor without- Interlocked Pipeline Stages (MIPS)processor is designed for the implementation of educational purposes, as well as it isexpected that this prototype of processor will be used for multimedia or big dataapplications. 32- bit MIPS processor was designed by using Very High speed HardwareDescription Language (VHDL). Pipelined MIPS processor contains three parts that are :data path 32-bit MIPS pipeline, control unit, and hazard unit. The single cycle MIPSsystem was subdivided into five pipeline stages to achieve the pipeline MIPS processor.The five parts include: instruction fetch (IF), Instruction Decode (ID), execution (EXE),memory (MEM) and Write Back (WB). Three types of hazard: data hazard , controlhazard and strctural hazard are resolved. Certain components in the pipelined stage forthe design processor were iterated for four core SIMD pipelined processors. The MIPS isdeveloped using Xilinx ISE 14.7 design suite. The designed processor was implementedsuccessfully on Xilinx Virtex-6 XC6VLX240T-1FFG1156 FPGA. The total poweranalysis of multi-core MIPS processor is obtanined 3.422 watt and the clock period was7.329 ns (frequency: 136.444MHz).

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