A Stego-analysis Techniques by SOD Using Statistical Measurements Based on FPGA


Abstract – Steganalysis is the technique of analyzing a stego-image to determine whether it has embedded data or not. More deliberately steganalysis, it can be achieved by coding a program that examines the stego-image structure and measures its statistical properties. This paper presents a novel steganalysis algorithm by detecting the sequence occurrence distribution (SOD) of cover/setgo-image using three types of statistical randomness properties tests: Frequency, Serial and Poker. Where hidden a 2.4Х10-7% distortion of covering image in multiple-LSB (MLSB), the difference achieved detection between cover-stage images as; frequency is 0.91362828; serial is 3.45887 and poker is 160.6455. Also, this proposed algorithm can point to the occurrences of the sequence which is affected by the embedded message, then implemented it by using 8-bit pair code and made by Xilinx-spartan-3A XC3S700AFPGA, with 50 MHz internal clock.