Design of Hierarchical Architecture of Multilevel Discrete Wavelet Transform Using VHDL Language


The wide spread of devices that use image processing in itsfunctions, like cellular phone and digital cameras, increases the need forspecialized processors for these functions as a replacement for softwareprograms that consume more time and resources. This paper presents ahardware description for discrete wavelet transform (DWT) module inVHDL language. The design involves the forward DWT (fDWT) and itsinverse (iDWT) characterized by variable number of transformation levels,ranging from one level to seven levels. Each one of these two modules isdesigned as hierarchical scheme that uses one-dimensional processingmodule twice to represent two-dimensional processing. The module can beused repeatedly on the same image for multilevel processing. Threeversions of the design are presented (v64, v128 and v256), each oneadapted different image size. Synthesis process showed that the designfrequency is about 56MHz. The simulation process showed that themaximum possible rounding error is about 0.012%. This resolution with thevariable number of processing level adapts this design to fit in manyapplications. Finally, a comparison of the proposed design with otherrelated work is presented, considering performance and specifications.