FPGA Simulation of Type-3 Feistel Network of The 128 bits Block Size Improved Blowfish Cryptographic Encryption


Reprogrammable devices such as Field Programmable Gate Arrays (FPGAs)are highly attractive options for hardware implementations of encryption algorithmsas they provide cryptographic algorithm agility, physical security, and potentiallymuch higher performance than software solutions , therefore this paper investigates ahardware design to efficiently implement block ciphers in VHDL based on FPGA’s.This hardware design is applied to the new secret-key block cipher called 128-bitsimproved Blowfish is proposed which is an evolutionary improvement of 64-bitsBlowfish designed to meet the requirements of the Advanced Encryption Standard(AES) to increase security and to improve performance. The proposed algorithm willbe used a variable key size up to 192 bytes. It is a Type-3 Feistel network iteratedsimple function 16 times.The resources used to implement the design just described are: the VHDLhardware description language, an FPGA platform from Xilinx and the XilinxSynthesis Technology (XST) software synthesis tools that belong to ISE 9.2i package.The device of choice is the XCV600-4fg680 belonging to the Virtex family ofdevices.In this paper, a pipeline and sequential methods are used to get a highthrougput (2.893Gbps) and a low area hardware design respectively.