Training Artificial Neural Networks by PSO to Perform Digital Circuits Using Xilinx FPGA


One of the major constraints on hardware implementations of Artificial NeuralNetworks (ANNs) is the amount of circuitry required to perform the multiplicationprocess of each input by its corresponding weight and there subsequent addition. FieldProgrammable Gate Array (FPGA) is a suitable hardware IC for Neural Network (NN)implementation as it preserves the parallel architecture of the neurons in a layer andoffers flexibility in reconfiguration and cost issues. In this paper the adaption of theANN weights is proposed using Particle Swarm Optimization (PSO) as a mechanismto improve the performance of ANN and also for the reduction in the ANN hardware.For this purpose we modified the MATLAB PSO toolbox to be suitable for the takenapplication. In the proposed design training is done off chip then the fully traineddesign is download into the chip, in this way less circuitry is required. This paperexecutes four bit Arithmetic Logic Unit (ALU) implemented using Xilinx schematicdesign entry tools as an example for the implementation of digital circuits using ANNtrained by PSO algorithm.