Performance Optimizing of Fourth Order Delta- Sigma Fractional-N Frequency Synthesizer using a Dither Technique for Third Generation (3G)

Abstract

This paper proposes a frequency synthesizer for WCDMA applications. Different techniques for phase noise reduction are discussed. Sigma-delta fractional-N technique is chosen for WCDMA system, since low settling time, spurious level and phase noise can be obtained by using this technique. Also it is proposed to add dither before the quantizer of modulator in order to eliminate any distortions introduced by the quantization stage. Design parameters for the proposed order (1-1-1-1) MASH fractional-N synthesizer for 3G are selected from the results of analysis for each unit of the proposed system and according to WCDMA standards. Simulation results prove that the proposed dithered frequency synthesizer for the WCDMA application is very efficient in reducing noise. The in-band phase noise obtained with this synthesizer is -96dBc/Hz. MATLAB (R2010a) are used for simulation of MASH (1-1-1-1) fractional-N frequency synthesizer.