Implementation of Golay Complementary Code Sequences Generator Based on FPGA

Abstract

Golay sequences have some properties make it distinctive in the applications and results. However, for this distinction must select the code sequences carefully and accurately. Therefore, to satisfy these requirements, a creation algorithm must be easy, accurate and powerful. In this paper, an FPGA based, design and implementation of Golay complementary code sequence(GCCS) creation and then made autocorrelation between their pair codes to verify properties. The process time for proposed algorithm is less than that for all possible algorithm by (1/4 to 1/1024 for 4-bit to 16 bits respectively). Thus, the Search can be regarded as pioneers of the research application of this technique to the subject and got good results. The Implementation was based on 8-bit pair code and made by Xilinx-spartan-3A XC3S700AFPGA, with 50 MHz internal clock.