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Article
Replacing the Hardware Addition Operation by Software algorithm without Carry
استبدال عملية الجمع بالبوابات بخوارزمية بدون استخدام تحميل

Author: Imad Matti Bakkow عماد متي بكو
Journal: Al-Ma'mon College Journal مجلة كلية المامون ISSN: 19924453 Year: 2013 Issue: 21 Pages: 277-285
Publisher: AlMamon University College كلية المامون الجامعة

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Abstract

This paper presents a new method to perform the arithmetic addition operation on numbers in a faster way in comparison with the existing one on computers. The proposed method builds a new architecture for the adder circuit in the CPU, So that there is no need for a waiting time to perform carrying bits from low order position to high order position when adding two numbers.The details of the new method are successfully tested with many different examples.

يقدم هذا البحث طريقة جديدة لتنفيذ عملية الجمع الحسابية على الاعداد بصورة أسرع مقارنة بما هو معتمد عليه في الحاسبات الالكترونية. تبني الطريقة المقترحة معمارية لدائرة الجامع( (adder circuitفي المعالج المركزي بحيث لا يعد هنالك حاجة الى وقت للانتظار (waiting time)، عند تنفيذ عملية التحميل(carry bit) من المرتبة السابقة للعدد الى المرتبة اللاحقة له عند جمع عددين.وقد تم اختبار تفاصيل الطريقة الجديدة بنجاح على امثلة عديدة مختلفة.


Article
Design of n-Bit Adder without Applying Binary to Quaternary Conversion

Authors: Walaa MH. Khalaf --- Dhafer Zaghar --- Kadhum Al-majdi
Journal: Engineering and Technology Journal مجلة الهندسة والتكنولوجيا ISSN: 16816900 24120758 Year: 2019 Volume: 37 Issue: 3 Part (A) Engineering Pages: 106-111
Publisher: University of Technology الجامعة التكنولوجية

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Abstract

Abstract- Microprocessor has been considered as most important part inICs manufacturing and making progress since more than 50 years, soincreasing microprocessor speed is paid attention in all technologies. ALUis known as the slowest part in microprocessor because of the ripple carry,nowadays microprocessor uses 8-uints as pipeline, each one has 8-bits forimplementing 64-bit, working in this form has been captured themicroprocessor development and limited its speed for all its computations.Parallel processing and high speed ICs always trying to increase this speedbut unfortunately it remains limited. The contemporary solution forincreasing microprocessors speed is the Multiple Valued Logic (MVL)technology that will reduce the 8-bits to 4-qbits, this paper proposes a newdesign of a 2-qbit full adder (FA) as a basic unit to implement MVL ALU(AMLU) that has 8-units as pipeline, each one consists of 4-qbits toimplement 32-qbit which is equivalent to 64-bit, without applying binary toquaternary conversion and vice versa. The proposed design increasesmicroprocessors speed up to 1.65 times, but also a little increase ofimplementation


Article
Design of Software Approach for Speeding up Addition Arithmetic Operation
تصميم طريقة برمجية لتسريع عملية الجمع الحسابية

Author: Imad Matti Bakko
Journal: Engineering and Technology Journal مجلة الهندسة والتكنولوجيا ISSN: 16816900 24120758 Year: 2013 Volume: 31 Issue: 3 Part (B) Scientific Pages: 381-390
Publisher: University of Technology الجامعة التكنولوجية

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Abstract

This paper presents a new method to perform arithmetic addition operation on numbers in a faster way in comparison with the exist one on computers.The proposed method builds a new architecture for the Adder Circuit in the CPU, which does not perform any carry operations. In fact, there is no need for a waiting time to perform carrying bits from low order positions to high order positions when adding two numbers.The new method is successfully tested with many different examples.

يقدم هذا البحث طريقة جديدة لتنفيذ عملية الجمع الحسابية على الإعداد بصورة أسرع مقارنة بما هو معتمد عليه حاليا في الحاسبات الالكترونية.تقترح هذه الطريقة بناء معمارية دائرة الجامع (adder circuit) في المعالج المركزي , بحيث لا وجود فيها لعملية التحميل (carry), حيث لايعد هنالك حاجة إلى وقت للانتظار (waiting time) عند تنفيذ التحميل (carry bit) من المرتبة السابقة للعدد إلى المرتبة اللاحقة له وذلك عند جمع عددين.تم اختبار تفاصيل الطريقة الجديدة بنجاح على امثلة عديدة مختلفة.

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