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Design of Hierarchical Architecture of Multilevel Discrete Wavelet Transform Using VHDL Language
تصميم معمارية هيكلية لتحويل المويجة DWT متعدد المستويات بأستخدام لغة VHDL

Author: Waleed Fawwaz Shareef
Journal: Engineering and Technology Journal مجلة الهندسة والتكنولوجيا ISSN: 16816900 24120758 Year: 2010 Volume: 28 Issue: 7 Pages: 1350-1360
Publisher: University of Technology الجامعة التكنولوجية

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Abstract

The wide spread of devices that use image processing in itsfunctions, like cellular phone and digital cameras, increases the need forspecialized processors for these functions as a replacement for softwareprograms that consume more time and resources. This paper presents ahardware description for discrete wavelet transform (DWT) module inVHDL language. The design involves the forward DWT (fDWT) and itsinverse (iDWT) characterized by variable number of transformation levels,ranging from one level to seven levels. Each one of these two modules isdesigned as hierarchical scheme that uses one-dimensional processingmodule twice to represent two-dimensional processing. The module can beused repeatedly on the same image for multilevel processing. Threeversions of the design are presented (v64, v128 and v256), each oneadapted different image size. Synthesis process showed that the designfrequency is about 56MHz. The simulation process showed that themaximum possible rounding error is about 0.012%. This resolution with thevariable number of processing level adapts this design to fit in manyapplications. Finally, a comparison of the proposed design with otherrelated work is presented, considering performance and specifications.

مع انتشار الاجهزة الحديثة التي تتضمن وظائفها معالجة الصور الرقمية, كالهواتفالخلوية و اجهزة التصويرالرقمية, ازدادت الحاجة الى توفر معالجات متخصصة تقوم بهذهالوظائف كبديل للبرمجيات التي تستغرق وقتا و مواردا اكثر. هذا البحث يقدم وصفا للكيانالعكسي و DWT الامامي و DWT التصميم يتضمن .VHDL بلغة DWT المادي لوحدةيتميز بمقدار متغير لعدد المستويات من واحد الى سبعة. كل وحدة منهما مصممة بصورةتركيبية من وحدات اصغر تقوم بعملية معالجة احادية البعد لتكوين وحدة ثنائية البعد. هذه الوحدةيمكن استخدامها تكراريا على نفس الصورة لتوفير معالجة متعددة المستويات. صممت ثلاثةكل منها مخصصة لحجم صورة مختلف. عملية ( v و 128 v و 256 v نماذج مختلفة ( 6456 . عملية المحاكاة اظهرت ان اكبر MHz تحليل التصميم اظهرت ان تردد التصميم هو تقريباخطأ تقريبي ممكن هو بقيمة 0.012 %. ان الدقة العالية مع العدد المتغير لمستوى المعالجة يجعل هذا التصميم ملائما لكثير من التطبيقات. اخيرا يقدم البحث مقارنة بين التصميم المقترحمع تصاميم اخرى مشابهة من حيث الاداء و المواصفات.

Keywords

wavelet --- image coding --- VHDL


Article
Hardware Implementation of IT2FLC using FPGA for Control Applications

Authors: Waleed Fawwaz Shareef --- Saif Faris Abulhail --- Dr. Mohammed Y. Hassan
Journal: Al-Qadisiyah Journal for Engineering Sciences مجلة القادسية للعلوم الهندسية ISSN: 19984456 Year: 2018 Volume: 11 Issue: 1 Pages: 40-54
Publisher: Al-Qadisiyah University جامعة القادسية

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Abstract

Interval Type2 Fuzzy Logic Control (IT2FLC) has been applied to a number of industrial, medical, home and military applications. Hardware implementation of IT2FLC can be achieved in a number of ways. One of these ways is the use of a Field Programmable Gate Array (FPGA).In this paper, the design and implementation of an IT2FLC using FPGA has been presented. The proposed controller is of Mamdani type. It works in different structures (P/PI/PD/PID like IT2FLC) depending on two control lines, different number of triangular shape memberships (2-7) depending on three control lines, six tunable gains and within a range of sampling time of (0.01-1024) seconds. Three type reduction algorithms are used and it is found that the Enhanced Iterative Algorithm with Stop Condition (EIASC) produced the minimum reduction in FPGA size. Thus less execution time. The reduction size is about 75% than Karnick Mendel (KM) and is about 3% than Enhanced KM (EKM). Linear and nonlinear models are used to test the designed Controller. Gains are tuned manually to reach minimum overshoot, settling time and steady state error.Simulation and Implementation results showed that the proposed controller works in an efficient way under no-load, load and uncertainty in the nonlinear model parameters.

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