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Design of n-Bit Adder without Applying Binary to Quaternary Conversion

Authors: Walaa MH. Khalaf --- Dhafer Zaghar --- Kadhum Al-majdi
Journal: Engineering and Technology Journal مجلة الهندسة والتكنولوجيا ISSN: 16816900 24120758 Year: 2019 Volume: 37 Issue: 3 Part (A) Engineering Pages: 106-111
Publisher: University of Technology الجامعة التكنولوجية


Abstract- Microprocessor has been considered as most important part inICs manufacturing and making progress since more than 50 years, soincreasing microprocessor speed is paid attention in all technologies. ALUis known as the slowest part in microprocessor because of the ripple carry,nowadays microprocessor uses 8-uints as pipeline, each one has 8-bits forimplementing 64-bit, working in this form has been captured themicroprocessor development and limited its speed for all its computations.Parallel processing and high speed ICs always trying to increase this speedbut unfortunately it remains limited. The contemporary solution forincreasing microprocessors speed is the Multiple Valued Logic (MVL)technology that will reduce the 8-bits to 4-qbits, this paper proposes a newdesign of a 2-qbit full adder (FA) as a basic unit to implement MVL ALU(AMLU) that has 8-units as pipeline, each one consists of 4-qbits toimplement 32-qbit which is equivalent to 64-bit, without applying binary toquaternary conversion and vice versa. The proposed design increasesmicroprocessors speed up to 1.65 times, but also a little increase ofimplementation

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